Async AGP/PCI Clock
Possible values of an option:
The option description:
Defines, whether owe frequencies of buses AGP and PCI synchronously to change together with frequency of the front-side bus ([Disabled]), or buses AGP and PCI should clock independently from remaining buses ([Enabled]). The second variant is more preferable — you can fix normal working frequencies of buses AGP (66 MHz) and PCI (33 MHz) without dependence from a level of acceleration of the front-side bus.
Other options identical to destination: