Cache Bus ECC

5/5 - (20 votes)
5/5 - (20 votes)

Cache Bus ECC

Option name:

Cache Bus ECC

Possible values of an option:

[Enabled], [Disabled]

The option description:

Allows to include control of parity for the cache memory of the processor of the second level. For the first time support of control of parity appeared in Pentium II at passage to 100 MHz the bus. Switching-on of this option ([Enabled]) is raised by reliability, truth, at the expense of almost imperceptible falling of productivity. As well as any other option raising stability of operation of the computer, it should be included. If your processor does not support this mechanism parity check is necessary for ungearing ([Disabled]).

Other options identical to destination:

CPU L2 Cache ECC Checking

CPU Level 2 Cache ECC Check

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