Option name:
Chipset NA# Asserted
Possible values of an option:
[Enabled], [Disabled]
The option description:
Gives the chance to include the mechanism pipelining at which the chipset produces a signal of readiness of a new memory address before all data transferred in a current cycle, will be processed. Naturally, at switching-on ([Enabled]) the given option the general high-speed performance raises. But, if there were problems with stability of operation, alas, it is necessary to refuse this mode ([Disabled]).