DRAM Command Rate
Possible values of an option:
[1T Command], [2T Command], there can be a variant [Auto]
The option description:
Specifies a time delay at an exchange of commands between the controler of storage of a chipset (processor) and storage (parameter tCR in the access chart). Qualitative units of storage are capable to work at a time delay in  clock period ([1T], [1T Command]) if stable operation in this mode is not provided, install a time delay in  clock periods ([2T], [2T Command]) (this mode and is offered by default). Sometimes there is a variant [Auto] (value undertakes from chip SPD).
Other options identical to destination: