DRAM Idle Timer

4/5 - (17 votes)
4/5 - (17 votes)

DRAM Idle Timer

Option name:

DRAM Idle Timer

Possible values of an option:

[0 Cycle], [8 Cycle], [16 Cycle], [32 Cycle], [64 Cycle] and, probably, [Infinity]

The option description:

Shows an amount of clock periods during which all open pages of storage in the absence of calls to them will be closed. In other words, this time of a finding of a line of storage in the buffer amplifier after reading operation before its record reversely in appropriate cells. Then, at the next reversal to storage cell, two variants are possible — if it already is in the buffer amplifier the data will be считаны with minimum time delays if it there is not present it is necessary to spend an extra time for page closing, and only after that to begin reading process. To estimate influence of this parameter on high-speed performance it is difficult enough. At chaotic data reading from storage (for example, operation with databases) is optimal setting of minimum values (can be, except [0 Cycle] — 0 clock periods), at serial (we tell, handling of graphic files), on the contrary, provides the maximum speed holding of page opened in flow of a considerable quantity of clock periods (besides, except for extreme value — [Infinity]). But anyway, the difference makes, a maximum, percent shares so it is possible to leave offered in the majority of chipsets a time delay by default in [8 Cycle] (clock periods). Possible values — from [0 Cycle] (open pages of storage are closed at once after reading) to [16 Cycle], [32 Cycle] or, even, [64 Cycle]. In certain cases there is also a value [Infinity] — the page will not be closed the greatest possible time.

Other options identical to destination:

SDRAM Idle Timer

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