DRAM RAS# to CAS# Delay
Possible values of an option:
Depend on storage type, there can be a variant [Auto]
The option description:
Time delay between signals RAS and CAS at reversal to storage cell (parameter tRCD in the access chart). For SDRAM there are enough  clock periods, but for problem units of storage it can be demanded to increase this value to . If to speak about DDR SDRAM the time delay normally makes the same  or  clock periods. For DDR2 SDRAM values from  to  clock periods, and for DDR3 SDRAM — from  to  clock periods are characteristic. Some problem units of storage cannot work normally without setting certainly the worst values. Among possible values can be present and a variant [Auto] (the information undertakes from chip SPD).
Other options identical to destination: